Teaching activities
- Digital Signal Processors (Level M1, 24h, INSA/EII)
- Digital Signal Processing systems
- DSP architecture
- Fixed-Point arithmetic
- Software development for Digital Signal Processing systems
- Labs: IIR filter implementation,
- VHDL (Level L3, 14h, INSA/SGM)
- Introduction to VHDL
- Labs: Descriptioon in VHDL of a small hardware system
- Digital Systems (Level L3, 12h, INSA/EII)
- Labs: design of a small hardware system with Altera’s tool Quartus
- Labs: design of a small hardware system with Altera’s tool Quartus
- Embedded Processors (Level L3, 30h, INSA/EII)
- Labs: MSP430, mobile robot
- Labs: MSP430, mobile robot
- Design methodology (Level M1, 20h, INSA/EII)
- MCSE methodology
Past Teaching activities
- Embedded Processors (Level L3, 70h, Enssat)
- Architecture of embedded processor
- ARM 7 programmer’s model and instruction set
- Development of real-time embedded software
- Peripheral description
- Labs: ultrasound radar, mobile robot, optical heart-rate sensor
- Digital Systems (Level L3, 38h, Enssat)
- Introduction to digital systems (hardware & software)
- Combinatorial and sequential logic
- Programmable logic
- Labs: design of a small hardware system with Altera’s tool Quartus
- Digital Signal Processors (Level M1, 42h, Enssat)
- Digital Signal Processing systems
- DSP architecture
- Fixed-Point arithmetic
- Software development for Digital Signal Processing systems
- Labs: IIR filter implementation, FSK transceiver, frequency domain filter
- Embedded systems (Level M1, 18h, Enssat)
- Memory systems
- Communication interfaces (serial, USB, Ethernet)
- Labs: embedded web server, USB interface
- Real-time OS (Level M1, 32h, Enssat)
- Labs on VxWorks
- Labs on VxWorks
- Design methodology (Level M1, 20h, Enssat)
- SART methodology
- SART methodology
- Code optimization for DSP (Level M2, 10h, Enssat)
- Architecture of high-performance DSP
- Data and instruction level parallelism
- Compiler description
- Labs: code optimization on a VLIW DSP
- Embedded software for signal processing applications (M2R SISEA, 14h, ISTIC/Univ. Rennes I)
- Architecture of high-performance DSP
- Compiler description
- Optimization for traditional DSP/ASIP
- Optimization for high-performance DSP
- Fixed-point arithmetic
- System modeling
- Arithmetic for signal processing applications (Level M2, 4h, Institut Polytechnique de Bordeaux)
- Fixed-point arithmetic
- Fixed-point conversion